Flash converters are a particular type of analog-to-digital converter which can operate at extremely high speeds.
One prominent type of analog-to digital converter sequentially compares an analog input to a series of reference voltages until the reference voltage closest to the analog input voltage (within one least significant bit) is found. For instance, in a typical successive-approximation analog-to-digital converter, the analog input voltage is compared with a first reference voltage that is half the full scale range of the converter. If the analog input voltage is greater than the first reference voltage, then half of the first reference voltage is added to the first reference voltage to produce a second reference voltage. If the analog input is less than the first reference voltage, then half of the first reference voltage is subtracted from the first reference voltage to produce the second reference voltage. The second reference voltage is then compared to the analog input. The converter continues to add or subtract, as the case may be, smaller and smaller potentials to the reference voltage until the reference voltage matches the analog input voltage to within one LSB.
Flash converters can operate at substantially higher speeds than successive-approximation, or the like, converters because they compare the analog input voltage with every possible reference voltage simultaneously, all comparisons being done in parallel. Thus, the reference voltage which is closest to the analog input voltage is determined in the first and only comparison period.
FIG. 1 illustrates the circuitry of a typical parallel, or flash, converter. A typical n bit flash converter comprises 2.sup.n -1 input comparators, 14-1 through 14-m, where m=2.sup.n -1. One input of each comparator is coupled to the analog input signal 12. The other input of each comparator is coupled to a different reference voltage. The reference voltages are spaced apart one LSB of the converter's full scale range. The analog input signal 12 is simultaneously compared by the 2.sup.n -1 comparators with every possible digitized value of the n-bit comparator's full scale range. Typically, the 2.sup.n -1 reference voltages are supplied by a fixed reference voltage 16 equal to the full scale range of the converter, provided to the inputs of the comparators 14-1 through 14-m through a reference resistive ladder as generally illustrated at 18. The resistance values of the reference resistance ladder are chosen such that the drop across each resistor is one LSB of the full scale range of the converter. Thus, each comparator compares the analog input voltage with one reference value for every possible digital value in the full scale range of the converter. In accordance with typical comparator operation, the comparators output a first logic level if the reference input is greater than the analog input and a second logic value if the reference input is less than the analog input. For instance, in a 10-bit flash converter having 1023 comparators, if the analog input voltage is 5 volts and the full scale range of the converter is 10 volts, then the outputs of comparators 14 1 through 14-512 will be of a first logic value and the outputs of comparators 14-513 through 14-1023 will be of a second logic value. The value of the analog input 12 is given by the highest numbered comparator outputting the first logic value, or, alternately, by the number of comparators outputting the first logic value. The flash converter includes encoding logic 20 which receives the outputs of the comparators 14 as its inputs and encodes the data received therefrom into a 10-bit code digitally representing the value of the analog input. A Gray code is commonly used; however, any digital code is acceptable.
U.S. patent application Ser. No. 07/283,791 for a Parallel Analog-to-Digital Converter assigned to the same assignee as the present invention discloses a flash converter architecture requiring a greatly reduced number of input comparators. The disclosure of that application is incorporated herein by reference. That application discloses a flash converter architecture which provides double the resolution over standard flash converter architectures by interpolating reference voltages between the outputs of the input comparators (the input comparators comprise differential pairs). The architecture disclosed herein is similar to the prior art parallel flash converter discussed in application Ser. No. 07/283,791, except that an additional latch is provided between each pair of adjacent latches. These additional latches compare the output of each input comparator (or differential pair) with the inverted output of the adjacent input comparator. As explained in application Ser. No. 07/283,791, the analog input voltage at which the output of an input comparator and the inverted output of an adjacent input comparator cross, so as to cause a change of state in the latch to which these two signals are supplied, occurs exactly halfway between the resistive ladder reference voltages supplied to the two adjacent input comparators. In this manner, a bonus threshold exactly halfway between every pair of adjacent reference voltages on the reference resistive ladder is obtained, without the need for additional input comparators or taps on the reference resistive ladder.
High resolution flash converters, even those employing the architecture disclosed in Application Ser. No. 283,791, require an extremely large number of comparators and associated logic as compared to other types of analog to-digital converters. Further, high resolution flash converters suffer from degradation of certain performance characteristics because of their specific architecture. For instance, in high resolution flash converter architectures such as 10-bit converters requiring 1023 comparator inputs from each of the analog input and the reference ladder, the input capacitance is very high and often is in excess of 100 pF. Due to the large input capacitance, the analog input node signal is very difficult to drive at high frequencies with existing buffers. The addition of the series resistances of the reference resistive ladder between the analog input and the buffer can often allow the buffer to drive the highly capacitive load; however, this resistance causes other problems, such as harmonic distortion produced across the series resistance by the analog input's voltage dependent capacitance.
Also, the static and dynamic base current errors of 1023 comparators create harmonic distortion produced by the "bow" of the reference resistance ladder.
In flash converters, differential non linearity is also a frequent problem. High resolution flash converter chips are very dense due to the high device count. Often, the chip is processed with poor device matching, which leads to poor differential linearity.
Therefore, it is an object of the present invention to provide a flash converter architecture with reduced analog input capacitance.
It is a further object of the present invention to provide a flash converter architecture with reduced voltage-dependent capacitance at the analog input.
It is another object of the present invention to provide a flash converter architecture capable of operating at high speeds and with low distortion.
It is yet one more object of the present invention to provide a flash converter architecture with reduced base current error in the reference resistance ladder.
It is a further object of the present invention to provide a flash converter architecture with improved differential linearity.
In general, it is thus an object of the present invention to provide an improved flash converter.